Kenwood DV-5700 Service Manual page 17

8. Video Deinterlacer : FL12200(X35, IC700)
8-1 Port Function
Port No. Port Name
Test outputs
112,113 TEST(00, 01)
Test inputs
41,50,51,108
TEST(0~5)
109,111
Power Supply Connections(Not shown on Block diagram)
1,33,63,73,84,
95,105,114,123, VDD33
137,144,151,167
2,17,34,55,64,
74,85,96,106,
VSS
115,124,132,138,
145,152,159,168
43 AVSS
16,54,107,158 AVDD25
42 AVDD
Control Signals
49 RESETB
53 OE
56~58 IFORMAT(2~0)
59~61 OFORMAT(2~0)
44,45 DADDR(1,0)
46 MODE
47 SDA
48 SCL
40 PIXCLK
62 N/P/IN/OUT
Control Signals(contd.)
52 NOMEM
Input Signals
18~27 G/YIN(0~9)
6~15 B/CbIN(0~9)
28~32 R/CrIN(0~4)
35~39 R/CrIN(5~9)
3 HSYNCREFI
4 VSYNCREFI
5 FIELDIN
Output Signals
65~72 G/YOUT(2~9)
75,76 G/YOUT0,1
93,94 B/CbOUT8,9
97~104 B/CbOUT(0~7)
DV-5700/DVF-R9050/R9050-S
CIRCUIT DESCRIPTION
I/O
These pins are test outputs and should be left unconnected in
O
normal operation.
These pins are used for test purposes only and should always
-
be tied low for normal operation.
Pad Ring digital power connections. Connect to the digital +3.3
-
volt power supply and decouple to the digital ground plane.
- Ground connections. Connect to the digital ground plane.
Ground connection for the clock PLL circuits.
-
Connect to the digital ground plane.
Core Logic digital power connections. Connect to the digital +2.5 volt power
-
supply and decouple to the digital ground plane.
Analog power connections for the clock PLL circuit.
- Connect to a separately decoupled +2.5 volt power supply and decouple
directly to the AVSS pin.
Reset. When this input is set low it will reset all the internal registers
I
to the default states.
When this pin is set high the outputs of the FL12200 will be enabled ; when
O it is set low the outputs will be set into a high-impedance state.
I Input signal format control.
O Output signal format control.
The settings of DADDR(1,0) allow the device address of the control
- bus to be programmed to prevent conflict with the other devices
connected to the bus.
When this pin is set low the control bus will operate in the slave mode
- ; allowing the device to programmed from an external controller.
I 2-wire serial control bus data.
I/O 2-wire serial control bus clock.
I Pixel clock input. This clock is used to drive all the circuits in the FL12200.
I/O NTSC/PAL input or output.
I No memory mode control input.
I 10-bit green or luminance signal input bus.
I 10-bit blue or Cb chroma signal input bus.
I 10-bit red or Cr chroma signal input bus.
I Horizontal sync or reference.
I Vertical sync or reference.
I Field identifier input.
O Green or luminance output bus.
O Blue or Cb chrominance output bus.
Function
17