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NXP Semiconductors ISP1562 Application Note

Designing a hi-speed usb host pci adapter
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AN10050
Designing a Hi-Speed USB host PCI adapter using the
ISP1562, ISP1563
Rev. 04 — 1 November 2007
Document information
Info
Content
Keywords
isp1562; isp1563; usb; universal serial bus; host; pci adapter
Abstract
This document contains a description of the ISP1562/3 application
schematics and the PCB design recommendations.
Application note

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  Summary of Contents for NXP Semiconductors ISP1562

  • Page 1 ISP1562, ISP1563 Rev. 04 — 1 November 2007 Document information Info Content Keywords isp1562; isp1563; usb; universal serial bus; host; pci adapter Abstract This document contains a description of the ISP1562/3 application schematics and the PCB design recommendations. Application note...
  • Page 2: Contact Information

    For additional information, please visit: For sales office addresses, please send an email to: AN10050_4 Application note Designing a Hi-Speed USB host PCI adapter using ISP1562/63 4: it is 2.5 inches ± 0.1 inch, not ± 1 inch. Section Section 3.4.
  • Page 3: Introduction

    (HCs) that can be directly connected to a standard 32-bit, 33 MHz PCI bus. For the rest of this document, they will be known as ‘ISP1562/3’. The ISP1562/3 complies with PCI Local Bus Specification Rev. 2.2 and PCI Bus Power Management Interface Specification Rev.
  • Page 4: Description Of The Application Schematics

    The other possible position of JP1 selects PCI V for complete Power Management tests, including S3 notebook. Note that pins 3, 77, 98 and 100 of the ISP1562, and pins 6, 12 and 95 of the ISP1563 are connected to the PCB V ISP1562, and pins 104, 111, 120 and 128 of the ISP1563 are connected to the PCB power plane.
  • Page 5: Input Clock: Applies Only To The Isp1563

    CLKRUN# is implemented in the ISP1562 on pin 42 and in the ISP1563 on pin 52. This signal is targeted mainly for mobile system designs. CLKRUN is an I/O pin. It is used by the system to safely turn-off the PCI CLK for power saving, with acknowledgment from the ISP1562/3 according to a predefined protocol.
  • Page 6: Legacy Support: Applies Only To The Isp1563

    NXP Semiconductors are defined on pins 96 (SCL) and 97 (SDA) of the ISP1562, and pins 122 (SCL) and 123 (SDA) of the ISP1563, respectively. When not in use, these signals must be connected to ground using a pull-down resistor, typically 10 kΩ.
  • Page 7: Pcb Design Recommendations

    1.5 inches. • The length of the PCI clock signal from the PCI bus connector to the ISP1562/3 must be 2.5 inches ± 0.1 inch in length and must be routed to only one load. It must usually be ‘snaked’.
  • Page 8: Schematics

    PCI 3.3 V power plane. • The decoupling capacitors must be placed as close as possible to the ISP1562/3. A good choice is the four corners of the IC because these areas will not normally be occupied by traces or other components, according to the ISP1562/3 pinout.
  • Page 9 C/BE2# C/BE3# INTA# REQ# FRAME# TRDY# IRDY# DEVSEL# STOP# PERR# SERR# Fig 1. ISP1562 eval board schematic – top level interfaces AN10050_4 Application note Designing a Hi-Speed USB host PCI adapter using ISP1562/63 ISP1562_ES1 AD[31:0] PCICLK RST# RST# IDSEL IDSEL...
  • Page 10 1 nF 1 nF 1 nF 1 nF All capacitors should be placed as close as possible to the corresponding power pins. Fig 2. ISP1562 eval board schematic – ISP1562 3.3 V AUX BLM21PG221SN1 FB 1 HEADER 3 +3.3 V 4.7μF...
  • Page 11 PERR# PERR# SERR# SERR# SERR# C/BE1# C/BE1# C/BE1# AD14 AD12 AD10 AD[31:0] Fig 3. ISP1562 eval board schematic – PCI edge connector CON5 −12 V TRST +12 V +5 V +5 V +5 V INTA INTB INTC INTD +5 V...
  • Page 12 +5 V BUS 0.1 μF 47 μF / 10 V 100 pF Optional BLM31PG121SN1 BLM31PG121SN1 Fig 4. ISP1562 eval board schematic – port power control and ESD protection 560 Ω OUTB +5V_Standby 0.1 μF +5 V BUS 0.1 μF BLM41PG600SN1 0.01 μF...
  • Page 13 TRDY# PCICLK STOP# FRAME# DEVSEL# PERR# SERR# AD[31:0] Fig 5. ISP1563 eval board schematic – top-level interfaces AN10050_4 Application note Designing a Hi-Speed USB host PCI adapter using ISP1562/63 ISP1563_ES1 ISP1563_ES1.SCH C/BE0# C/BE1# C/BE2# C/BE3# TRDY# IDSEL IDSEL PME# PME#...
  • Page 14 DV AUX +3.3 V 0.1 μF 1 nF 0.1 μF 1 nF Should be placed Should be placed as close as as close as possible to pin 67 possible to pin 95 DV AUX DV AUX 0.1 μF 0.1 μF 0.1 μF 4.7 μF 0.1 μF...
  • Page 15 PCICLK PCICLK PCICLK REQ# REQ# REQ# AD31 AD29 AD27 AD25 C/BE3# C/BE3# C/BE3# AD23 AD21 AD19 AD17 C/BE2# C/BE2# C/BE2# IRDY# IRDY# IRDY# DEVSEL# DEVSEL# DEVSEL# PERR# PERR# PERR# SERR# SERR# SERR# C/BE1# C/BE1# C/BE1# AD14 AD12 AD10 AD[31:0] Fig 7. ISP1563 eval board schematic – PCI edge connector CON5 −12 V TRST...
  • Page 16 D VAUX 10 kΩ 10 kΩ PWE1# PWE1# ENB# OUTB OC1# OC1# FLGB# 10 kΩ 0.1 μF 0.1 μF OC2# FLGA# OC2# 10 kΩ PWE2# PWE2# ENA# OUTA MIC2526 10 kΩ 10 kΩ D VAUX +5 V BUS + C40 47 μF / 10 V 0.1 μF 47 μF / 10 V...
  • Page 17: Legal Information

    Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice.
  • Page 18: Table Of Contents

    Disclaimers...17 Trademarks ...17 Contents...18 Designing a Hi-Speed USB host PCI adapter using ISP1562/63 Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'. © NXP B.V. 2007. All rights reserved.

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