Schematic Diagram; Circuit Description; Smps Board; Logic Board - Samsung PS50Q91HX Service Manual

7. Schematic Diagram

7-1 Circuit Description

Logic Board

Input
Data
Data
Controller
Processor
LVDS
Main Board
LVDS Image
Deinterlacer
Trans Enhancer
CPU
Image
Decoder Decoder
Scaler
A/D
TMDS
Converter
Recever

■ SMPS Board

The SMPS used for the PDP has been designed to be efficient, compact and lightweight. For VS and VA outputs, a LLC converter
has been used. For the other outputs, a Flyback converter has been used.
■ LOGIC Board
The logic circuit consists of a Logic Main Board and an Address Buffer Board. The Logic Main Board decodes the video signal
encoded by the Video Board, outputs the ADDRESS data signal for each pattern and generates X and Y drive signals. The
Address Buffer Board buffers and transfers the ADDRESS data output signal using TCP IC.
- LVDS with built-in video signal processing (W/L, error diffusion, APC, FCR, etc.) applied and 1 ASIC chip.
- Outputs the address Drive IC control and data signals to the Buffer Board.
- Outputs the control signal for the X and Y Drive Boards.
- Monitors major drive voltages (Micom Circuit Block); detects if a surge voltage has been applied and protects the Drive Circuit.
- Temperature Adaptive Operating Mode (Low Temperature/Room Temperature/High Temperature); Discharge optimization for
each temperature level.
■ X-MAIN Board
Connects to the X terminal block, 1) provides maintaining voltage waveform (including ERC), and 2) maintains the Ve bias in the
Scan section.
■ Y-MAIN Board
Connects to the Y terminal block, 1) provides maintaining voltage waveform (including ERC), 2) provides Y Rising, Falling Ramp
waveforms, and 3) maintains the Vscan bias.
■ Address Buffer Board
It delivers the data signal and control signal to the TCP.
Samsung Electronics
Y Main Board
Display
DRAM
Data
Display
Driver
Timing
Timing
Generator
Controller
Scan
Timing
Audio
Processor
Video Speaker
Out
Tuner
Video
Micom
S/W
Row
PDP Panel
Driver
42" - 1024x768 Pixels
1024x768x3 Cells (R,G,B)
50" - 1365x768 Pixels
1365x768x3 Cells (R,G,B)
Y-Pulse
Address Buffer
SMPS Board
Main SMPS
Schematic Diagram
X Main Board
X-Pulse
Generator
AC Power
Source
7-1