Sony DVP-NS30 Servise Manual page 53

DVP-NS30/NS32/NS33/NS52P
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Pin No. Pin name
50 OCSW
51 EEWP
52 DVDD18
53 HA2
54 HA3
55 HA4
56 HA5
57 HA6
58 HA7
59 HA8
60 HA18
61 HA19
62 DVSS
63 APLLCAP
64 APLLVSS
65 APLLVDD3
66 xWR
67 HA16
68 HA15
69 HA14
70 HA13
71 HA12
72 HA11
73 DVDD3
TE
74 HA10
L 13942296513
75 HA9
76 HA20
77 xROMCS
78 HA1
79 xRD
80 DVDD3
81 HD0
82 HD1
83 HD2
84 HD3
85 DVSS
86 HD4
87 HD5
88 HD6
89 HA21
90 ALE
91 HD7
92 HD17
93 HA0
94 DVSS
95 UWR#
96 URD#
www
97 DVDD18
98 IFSDO
99 IFCK
100 xIFCS
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Type
Input Servo GPIO 1
Output EEPROM write Protect Control
Power 1.8V power pin for internal digital circuitry
Output PU Host address bit2
Output PU Host address bit3
Output PU Host address bit4
Output PU Host address bit5
Output PU Host address bit6
Output PU Host address bit7
Output PU Host address bit8
Output SMT Host address bit18
Output SMT Host address bit19
Ground Ground pin for internal digital circuitry
Analog Input APLL External Capacitance connection
Ground Ground pin for audio clock circuitry
Power 3.3V power for audio clock circuitry
Output SMT Write enable, active Low
Output Host address bit16
Output PU Host address bit15
Output PU Host address bit14
Output PU Host address bit13
Output PU Host address bit12
Output PU Host address bit11
Power 3.3V power pin for internal digital circuitry
Output PU Host address bit10
Output PU Host address bit9
Output SMT Host address bit20
Output PU, SMT Chip select, active Low
Output PU Host address bit1
Output SMT Read enable, active Low
Power 3.3V power pin for internal digital circuitry
Output Host data bit0
Output Host data bit1
Output Host data bit2
Output Host data bit3
Ground Ground pin for internal digital circuitry
Output Host data bit4
Output Host data bit5
Output Host data bit6
Output SMT Host data bit21
Output PU,SMT Address latch enable
Output Host data bit7
Output Host address bit17
Output PU Host address bit0
Ground Ground pin for internal digital circuitry
Output PU,SMT 8032 write strobe
Output PU,SMT 8032 read strobe
Power 1.8V power pin for internal digital circuitry
Output PU,SMT
x ao
y
Default High Ext. CPU Serial data output (H/W method)
Output PU,SMT
. i
Default High Ext. CPU Serial clock (H/W method)
Output PU,SMT
Default High Chip select for Ext.CPU (Low Active, H/W method)
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8
Function
Q Q
3 6 7 1 3
u163
.
5-2
2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
m
co
9 9
2 8 9 9