Sanyo DC-DA70 Service Manual page 14

Micro component system
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IC BLOCK DIAGRAM & DESCRIPTION
IC602 LC78622E (Digital Signal Processor)
No. Pin Name I/O
1
DEFI
I Input terminal for detect signal of defect
2
TAI
I Input terminal for test.
3
PDO
O The phase comparison output terminal for
external VCO control.
4
VVSS
- Ground terminal for built-in VCO
5
ISET
I Resistance connection terminal for
electric current adjustment of PDO output.
6
VVDD
- Built-in VCO power supply terminal.
7
FR
I VCO frequency range adjustment.
8
VSS
- Ground for Digital
9
EFMO
O EFM signal output terminal for slice level control.
10
EFMIN
I EFM signal input terminal for slice level control.
11
TEST2
I TEST pin. Normal time is non connection.
12
CLV+
O Output terminal for Disc motor control.
13
CLV-
O Output terminal for Disc motor control.
14
V/P
O Change of rough servo / phase control
Rough servo : "H", Phase control : "L"
15
HFL
I Input terminal of track search signal.
16
TES
I Input terminal of tracking error signal.
17
TOFF
O Output terminal of tracking off.
18
TGL
O Output terminal for change of tracking gain.
19
JP+
O Output terminal for tracking jump control.
20
JP-
O Output terminal for tracking jump control.
21
PCK
O Clock monitor output terminal for EFM data
playback. (4.3218 MHz)
22
FSEQ
O Output terminal for detect of SYNC signal.
23
DVDD
- +5V
24
CONT1
I/O
25
CONT2
I/O This output can control at serial control from
26
CONT3
I/O micro processor.
27
CONT4
I/O
28
CONT5
I/O
29
EMPH
O Output terminal of de-emphasis monitor .
"H" : de-emphasis
30
C2F
O Output terminal of C2 flag
31
DOUT
O Output terminal of digital out
SQOUT
Function
EFMO
VVDD VVSS
PDO ISET FR
9
6
4
1
DEFI
Slice level
VCO Clock Oscillator
Control
& Clock Control
EFMIN
10
Syncrnous Detect
22
FSEQ
EFM Demodulation
CLV+
12
CLV
Digital Servo
13
CLV-
14
V/P
PW
49
SBCK
51
Subcode Dxract
47
SBSY
QCRC
50
SFSY
63
CS
WRQ
53
COM
Inter Fase
55
57
CQCK
COIN
56
Servo Commander
54
RWC
15
16
17
20
19 58
18
24 25 26 27 28
HFL
TES
TOFF
JP-
JP+
RES
TGL
CONT1
No. Pin Name I/O
32
TEST3
33
TEST4
34
NC
35
MUTEL
36
LVDD
37
LCHO
38
LVSS
39
RVSS
40
RCHO
41
RVDD
42
MUTER
43
XVDD
44
XOUT
45
XIN
46
XVSS
47
SBSY
48
EFLG
49
PW
50
SFSY
51
SBCK
52
FSX
53
WRQ
54
RWC
55
SQOUT
56
COIN
57
CQCK
58
RES
59
TST11
60
16M
61
4.2M
62
TEST5
63
CS
64
TEST1
TST11
TEST2
TEST4
TAI
TEST1
TEST3 TEST5
PCK
21
2 59 64 11 32 33 62
3
5
7
2K~8bit
RAM
C1 C2 Error Detect &
Correct Control Flag
X'tal Root
General Ports
Timing Generator
29
48
60
61 46 52 45 44 43
CONT3
CONT5
EMPH
EFLG
16M
4.2M
FSX
XIN
CONT2
CONT4
XVSS
XOUT
- 13 -
Function
I Test pin.
I Test pin.
- Non connection.
O Mute output terminal for L-ch
- Power supply for L-ch
O Output terminal for L-ch
- GND for L-ch
- GND for R-ch
O Output terminal for R-ch
- Power supply for R-ch
O Mute output terminal for R-ch
- Power supply of crystal oscillation
O Connection terminal of crystal oscillation (16.9344MHz)
I Connection terminal of crystal oscillation (16.9344MHz)
- GND of crystal oscillation
O Output terminal for synchronizing signal of
sub-cord block
O Output terminal for correction monitor of C1, C2,
Single and Double
O Output terminal for sub-cord of P, Q, R, S, T, U and W
O Output terminal for synchronizing signal of
sub-cord frame
I Input terminal for readout clock of sub-cord
O Output terminal of Synchronizing signal (7.35kHz)
O Output terminal for standby of sub-cord Q output
I Input terminal of read / write control
O Output terminal of sub-cord Q
I Input terminal of command from micro processor
I Clock input for reading sub-cord from SQOUT
I Reset (turn on : L)
O Test pin
O 16.9344MHz
O 4.2336MHz
I Test pin
I Chip select terminal
I Test pin
VDD VSS
23
8
RAM Address
Generatorl
Interpolalation Mute
30
Billingual
Digital Out
31
Digital Attenuator
Quadruple Over Sampling
Digital Filter
34
1bit DAC
L.P.F
39 41
42
40
37
35
38
36
XVDD
RVDD
RCHO
LCHO
MUTEL
LVDD
RVSS
MUTER
LVSS
C2F
DOUT
(NC)

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