Pioneer DVR-231-S Service Manual page 71

5
QQ
3 7 63 1515 0
UPD61181F1-101MN2A (MAIN ASSY : IC1001)
(EMMA2RL)
• 1 Chip System Codec
Block Diagram
CVBS or Y/C
DV
MPEG-TS
BT.656
Stream
TE
L 13942296513
[Each Block]
1. MAIN CPU
CPU of 187MHz, 32bit, MIPS32
Attached with EJTAG debugger interface
2. Sub CPU
CPU of MIPS32
Operating for DSP section
3. Memory Controller
Correspond to DDR ×2 of 128Mbit – 512Mbit
Frequency is up to PC333(166MHz ×2)
4. ROM Interface (EMI)
FLASH ROM interface
5. GIO (EMI)
PCMCIA, etc
6. Peripheral
Universal input/output interface
Communication with TUFL-con
Watch-dog timer
7. Video Decoder
VDEC of 240MHz/10bit
Input is only YC 2ch, or V.
3D Y/C separation, 3D noise filter
Video signal
www
input
.
5
http://www.xiaoyu163.com
6
CPU
Video
MIPS32
Decoder
1394 Link
MPEG
AV
Encode
DV decode
AV
Switch
Y/C separation
Video siganl
processing
Input block
x ao u163
y
i
6
http://www.xiaoyu163.com
2 9
8
Ext. Memory
DDR33
Unified
Memory
Controller
Stream
Processor
CSS/CPRM etc.
1st 2nd
ATA ATA
Peripheral
DVD
HDD
Q Q
3 6 7 1 3
8. MPEG AV Encoder
Video : MPEG1, 2
Audio : MPEG1, 2 Conversion to LPCM
9. Stream processor
Interface of stream
Decription of CSS, CPRM
En/Decription of CPRM, DES
10. MPEG Decoder
Video : MPEG1, 2, JPEG
This decoder is able to decode 2 signals simultaneously.
Audio : MPEG1, 2, LPCM, MP3, WMA, Dolby-digital
Test tone, Virtual surround
5.1ch Dolby-digital(option)
11. Video Encoder
Video DAC of 554MHz/10 bit
Correspond to 5ch Y, Pb, Pr(RGB, Component), YC(CVBS) of
NTSC/PAL/SECAM
VBI
detection
Color
block demodulation
Clock generator
.
DVR-231-S
7
9 4 2 8
CPU
Video
MIPS32
Encoder
Display
MPEG
Controller
Video
&
Decode
Scaler
Audio
Processor
1 5 0 5 8 2 9 9 4
Clock
Conversion
Video signal
m
processing
output block
block
co
I2C register
7
8
9 9
A
480P
B
480I
BT.656 or
BT.1358
PCM
S/PDIF
C
2 8 9 9
D
E
Video signal
output
F
71
8