LG 42LB5800 Service Manual page 30

M13 EAX64872104 BASE
14y Smart TV
IC100-*1
M24256-BRMN6TP
NVRAM
+3.3V_NORMAL
E0 VCC
1 8
E1 WC
2 7
E2 SCL
3 6
IC100 +3.3V_NORMAL VSS SDA
R101 R102 4 5
4.7K 4.7K AT24C256C-SSHL-T
OPT
NVRAM_ST
R100
A0 VCC
1 8 Write Protection
4.7K
A1 WP - Low : Normal Operation
OPT
2 7
- High : Write Protection
A2 SCL
R135 33
3 6
GND SDA
R134 33
4 5
NVRAM_ATMEL
HDCP EEPROM
Deleted
I2C
R147-*1 R142-*1
TU_Q_SG TU_Q_SG
1.5K
1.5K
R121 R124 R132 R133 R138 R141
1.2K 1.2K 2.7K 2.7K 2.7K 2.7K
R120 33
STB_SCL
R115 33
STB_SDA
R116 33
OPCTRL_11_SCL
R117 33
OPCTRL_10_SDA
R118 33
OSCL1
R119 33
OSDA1
R110 33
OSCL2
R111 33
OSDA2
R112 33
OSCL0
R113 33
OSDA0
R114 33
OPCTRL_1_SCL
R109 33
OPCTRL_0_SDA
Model Option
+3.3V_NORMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
M13 PCB P/NO
EAX64797001* : LD33B
EAX64872101* : LA33B
NC4.5 PCB P/NO
NON CI : EAX65610201
CI :
I2C_SCL5
I2C_SDA5
+3.3V_NORMAL
R155 R162 R163
R157
OPT
1K 1K 1K 1K
LED_PWM0
LED_PWM1
OPCTRL3
OPCTRL7
R156
R154 R160
R161
1K
1K OPT 1K OPT
1K
I2C_1 : AMP, L/DIMMING,HDCP KEY
I2C_2 : T-CON,
I2C_3 : MICOM
I2C_4 : S/Demod,T2/Demod, LNB, MHL(Sil1292)
I2C_5 : NVRAM
I2C_6 : TUNER_MOPLL(T/C,ATV)
+3.3V_NORMAL
R152-*1 R153-*1
TU_Q_KR TU_Q_KR
1.5K
1.5K
R142 R147 R152-*2 R153-*2
R150 R151
R152 R153
2.7K 2.7K 2.7K 2.7K
2.7K 2.7K TU_N_TW/BR TU_N_TW/BR
1.2K 1.2K
I2C_SCL1
I2C_SDA1
M13 vs Lean Smart
I2C_SCL2/SDA2
del. I2C_SCL2/SDA2
cause of EPI block deletion
I2C_SCL_MICOM
I2C_SDA_MICOM
I2C_SCL4
I2C_SDA4
I2C_SCL5
I2C_SDA5
I2C_SCL6
I2C_SDA6
MODEL_OPT_0
Country_TW
MODEL_OPT_0
MODEL_OPT_1
MODEL_OPT_1 FRC
MODEL_OPT_2
MODEL_OPT_2 Panel
MODEL_OPT_3
Country_AJJA
MODEL_OPT_3
/S2_RESET MODEL_OPT_4
MODEL_OPT_4 Module
MODEL_OPT_5
MODEL_OPT_5 DDR
MODEL_OPT_6
CP BOX
MODEL_OPT_7 MODEL_OPT_6
MODEL_OPT_7
MODEL_OPT_8
T2 Tuner
MODEL_OPT_9
MODEL_OPT_8 S Tuner
MODEL_OPT_10
MODEL_OPT_9
DDR
M13 vs Lean Smart
MODEL_OPT_10 EPI
Option Name change
DDR_1.25G
MODEL_OPT_5
High
MODEL_OPT_9
Low
STRAPPING LED_PWM0 LED_PWM1 OPCTRL3
ICE mode + 27M + serial boot 1 0 0
ICE mode + 27M + ROM to Nand boot 1 0 0
ICE mode + 27M + ROM to 60bit ECC Nand boot 1 0 1
ICE mode + 27M + ROM to eMMC boot from 1 0 1
EMMC pins (share pins w/s NAND)
ICE mode + 27M + ROM to eMMC 1 1 0
Boot from SDIO pins
CI_ADDR[0-14]
SOC -> CI SLOT
MT5398_MCLKI
MT5398_MIVAL_ERR
MT5398_MISTRT
SOC -> CI SLOT
MT5398_TS_OUT[0-7]
CI_DATA[0-7]
CI SLOT -> SOC
GPIO45(EMMC_RST) is dedicated to reset
HIGH LOW
EMMC for improving A1's leakage current
TW
Non_TW
/USB_OCD2
FRC(120Hz) No FRC(60Hz)
/USB_OCD1
/USB_OCD3
FHD HD
EMMC_RST
AJJA Non_AJJA USB_CTL1
V13 V12 #SIL_RESET
M13 vs Lean Smart
DDR_1.25G DDR_1.5G
del. EPI_LOCK6
Enable Disable
cause of EPI block deletion
Support Not Support
Support
Not Support
SC_ID_SOC
DDR_0.78G NON_DDR_0.78G
M13 vs Lean Smart
OPT
Default Option Name change
Support to Opt
Not Support to Deafult
USB_CTL3
DDR_1.5G DDR_0.768G
Low High
Low High
C114-*2
3.3pF
50V
EAX6558850X_3.3pF
EAX6558850X_3.3pF
X-TAL
MT5398_XTAL_IN
Close to eMMC Flash C114
(IC8100) EAX6561090X_1pF 1.0pF
50V
EMMC_CLK
R168
10K
VDD3V3
LGE2122[A2_M13]
AK10
L/DIM0_MOSI JTCK
AK11
L/DIM0_SCLK JTDI
AL9
JTDO
AJ11
JTMS
AJ12
L/DIM0_VS JTRST
AH11
OSDA0 OSDA0
AH10
OSCL0 OSCL0
AF11
OSDA1 OSDA1
AG11
OSCL1
OSCL1
AN29
AVDD_33SB
MT5398_XTAL_IN
XTALI
AM29
MT5398_XTAL_OUT XTALO
AN30
OPCTRL7
AVDD33_XTAL_STB
C111 AL29
AVSS33_XTAL_STB
0
0.1uF
1
AVDD_33SB
0
AN17
AVDD33_VGA_STB
C110 AL17
1
AVSS33_AVSS33_VGA_STB
0.1uF
VDD3V3
0
AL26
AVDD33_PLL
C109 AC21
0.1uF AVSS33_PLLGP
H21
AVSS33_CPUPLL
AM17
AVDD10_LDO
C107
4.7uF
10V
AN16
AVDD10_ELDO
C112
4.7uF
10V
IC105
LGE2122[A2_M13]
CI_ADDR[0-14]
CI_ADDR[0] B30 P30
GPIO0 DEMOD_RST
CI_ADDR[1] A31 N32
GPIO1 DEMOD_TSCLK
CI_ADDR[2] B31 R27
GPIO2 DEMOD_TSDATA0
CI_ADDR[3] A32 T26
GPIO3 DEMOD_TSDATA1
CI_ADDR[4] C30 T27
GPIO4 DEMOD_TSDATA2
CI_ADDR[5] A33 P26
GPIO5 DEMOD_TSDATA3
CI_ADDR[6] B32 R28
GPIO6 DEMOD_TSDATA4
CI_ADDR[7] C31 U27
GPIO7 DEMOD_TSDATA5
CI_ADDR[8] E30 U26
GPIO8 DEMOD_TSDATA6
CI_ADDR[9] F29 R26
GPIO9 DEMOD_TSDATA7
CI_ADDR[10] F27 R29
GPIO10 DEMOD_TSSYNC
CI_ADDR[11] F28 P27
GPIO11 DEMOD_TSVAL
CI_ADDR[12] C32
GPIO12
CI_ADDR[13] F30 L25
GPIO13 CI_INT
CI_ADDR[14] F32 N33
GPIO14 CI_TSCLK
D30 K26
GPIO15 CI_TSDATA0
D32 N30
GPIO16 CI_TSSYNC
F31
N31
GPIO17 CI_TSVAL
MT5398_TS_OUT[0] F33
GPIO18
MT5398_TS_OUT[1] E31 M31
GPIO19 PVR_TSCLK
MT5398_TS_OUT[2] E32 M27
GPIO20 PVR_TSVAL
MT5398_TS_OUT[3] D31 L27
GPIO21 PVR_TSSYNC
MT5398_TS_OUT[4] D33 M29
GPIO22 PVR_TSDATA0
MT5398_TS_OUT[5] E29 M30
GPIO23 PVR_TSDATA1
MT5398_TS_OUT[6] C33
GPIO24
MT5398_TS_OUT[7] B33 L30
GPIO25 SPI_CLK1
CI_DATA[0] A30 L33
GPIO26 SPI_CLK
CI_DATA[1] E28 L32
GPIO27 SPI_DATA
CI_DATA[2] C29 K27
GPIO28 SPI_CLE
CI_DATA[3] J28
GPIO29
CI_DATA[4] H29 AL8
GPIO30 OPWM2
CI_DATA[5] J26 AM8
GPIO31
OPWM1
CI_DATA[6] G30 AM9
GPIO32 OPWM0
CI_DATA[7] G27
GPIO33
E27 D27
MT5398_TS_IN[0]
GPIO34 SD_D0
D29 C27
MT5398_TS_IN[1]
GPIO35 SD_D1
D28 D26
MT5398_TS_IN[2]
GPIO36 SD_D2
H28 C26
MT5398_TS_IN[3]
GPIO37 SD_D3
J27 A28
MT5398_TS_IN[4]
GPIO38 SD_CMD
G29 E24
MT5398_TS_IN[5]
GPIO39 SD_CLK
G31
MT5398_TS_IN[6]
GPIO40
G28
MT5398_TS_IN[7]
GPIO41
B28
GPIO42
K28
GPIO43
E25
GPIO44
D21
GPIO45
G23
GPIO46
C28
GPIO47
F24 AF15
EPI_LOCK6
GPIO48 LED_PWM1
AB8 AG15
CTS
GPIO49 LED_PWM0
AA7
RTS GPIO50
AD6
OTP_WRITE
GPIO51
AC8
MODEL_OPT_3 GPIO52
AC7 AL16
MODEL_OPT_7
GPIO53 OPCTRL11
AB6
AM16
MODEL_OPT_5 GPIO54 OPCTRL10
AC6 AE17
MODEL_OPT_6
GPIO55 OPCTRL9
NON_EU AG19
OPCTRL8
R169 10K
AJ23 AH17
ADIN0_SRV OPCTRL7
R170 10K AH23 AE19
ADIN1_SRV OPCTRL6
AE28 AH19
ADIN2_SRV OPCTRL5
AD28 AK16
MODEL_OPT_0
ADIN3_SRV OPCTRL4
AF22 AG17
M_RFModule_RESET ADIN4_SRV OPCTRL3
AK21 AJ17
OPC_EN
ADIN5_SRV OPCTRL2
AG24 AF19
/TU_RESET1 ADIN6_SRV OPCTRL1
AM18 AJ19
MODEL_OPT_4 /S2_RESET ADIN7_SRV OPCTRL0
C115-*2 C114-*1
C115-*1
3.3pF 2.7pF
2.7pF
50V 50V 50V
EAX6561020X_2.7pF EAX6561020X_2.7pF
X100
27MHz
X-TAL_1 GND_2
1 4
GND_1 X-TAL_2
2 3 MT5398_XTAL_OUT
C115
EAX6561090X_1pF
1.0pF
50V
M13 vs Lean Smart
del. FE_LNA_Ctrl1/2
cause of Tuner change 13y to 14y
IC105
+3.3V_NORMAL
AH15
U0TX SOC_TX
AH14
SOC_RX R183 R184
U0RX
4.7K 4.7K
AH13
U1TX
M_REMOTE_TX
AG13
M_REMOTE_RX
U1RX
D24
POWE EMMC_CMD
B25
POOE
D25 FE_LNA_Ctrl1/2
EMMC_DATA[2-7]
POCE1
A25
POCE0
EMMC_DATA[7]
C22
PDD7 EMMC_DATA[6]
B22
PDD6
EMMC_DATA[5]
A22
PDD5 EMMC_DATA[4]
C23 AVDD_33SB
PDD4
EMMC_DATA[3]
Wake On Lan A23 CAM_SLIDE_DET
PDD3 EMMC_DATA[2]
B23
R188
PDD2
D23 4.7K
PDD1
C24
PDD0
WOL/ETH_POWER_ON
C25 CAM_SLIDE_DET
PARB R187
A26
4.7K
EMMC_DATA[1]
PACLE
B26 OPT
+3.3V_NORMAL
PAALE EMMC_DATA[0]
C21
EMMC_CLK
EMMC_CLK
R158
R189
AL15
10K
OPWRSB
OPT
22 R186
AK20
ORESET
22 C117
AF17
0.1uF
OIRI
16V
C20
FSRC_WR
AL14
+3.3V_NORMAL
STB_SCL STB_SCL
Q100
AK15 D100
STB_SDA R196 PMV48XP
STB_SDA 1N4148W
240
R193 4.7K
AE14
100V
POR_BND
G
OTP_WRITE
FE_DEMOD1_TS_DATA[0-7]
PCM_RST
FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_DATA[0]
FE_DEMOD1_TS_DATA[1]
FE_DEMOD1_TS_DATA[2]
FE_DEMOD1_TS_DATA[3]
FE_DEMOD1_TS_DATA[4] EXTERNAL DEMOD
-> SOC
FE_DEMOD1_TS_DATA[5]
FE_DEMOD1_TS_DATA[6]
FE_DEMOD1_TS_DATA[7]
FE_DEMOD1_TS_SYNC
FE_DEMOD1_TS_VAL
/PCM_REG
/PCM_CE1
MT5398_TS_SYNC
CI SLOT -> SOC
/PCM_WE
/PCM_OE
MT5398_TS_VAL
CI SLOT -> SOC
CI_A_VS1
MT5398_TS_CLK CI SLOT -> SOC
/PCM_IRQA
/PCM_WAIT
+3.3V_NORMAL
/CI_CD2
/CI_CD1
/PCM_IORD R174 R177
4.7K
4.7K
/PCM_IOWR
OPT OPT
R179 PWM_DIM2
PWM_DIM2
22
PWM_DIM1
R178 22
/RST_HUB
R173 R176
/RST_HUB
1K
1K
PWM2_PULL_DOWN_1K
PWM1_PULL_DOWN_1K
SMARTCARD_CLK/SD_EMMC_DATA[0]
SMARTCARD_CLK/SD_EMMC_DATA[0]
SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]
SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]
SMARTCARD_RST/SD_EMMC_DATA[2]
SMARTCARD_RST/SD_EMMC_DATA[2]
SMARTCARD_DET/SD_EMMC_DATA[3]
SMARTCARD_DET/SD_EMMC_DATA[3]
SMARTCARD_VCC/SD_EMMC_CMD
SMARTCARD_VCC/SD_EMMC_CMD
SMARTCARD_DATA/SD_EMMC_CLK
SMARTCARD_DATA/SD_EMMC_CLK
LED_PWM1
LED_PWM0
5V Tolerance
OPCTRL_11_SCL
OPCTRL_10_SDA
COMP1_DET
SC_DET
OPCTRL7
HP_DET
AV1_CVBS_DET
AMP_RESET_SOC
OPCTRL3
R182
RF_SWITCH_CTL AMP_RESET_SOC AMP_RESET_N
33
OPCTRL_1_SCL
R185
OPCTRL_0_SDA
10K
MID_MAIN_1 2013.07.16
508
LGE Internal Use Only
SOC_RESET