Sony HCD-SR4W Service Manual page 97

QQ
3 7 63 1515 0
DMB08 BOARD IC801 CXD2753R (DSD DECODER)
Pin No. Pin Name
1
2 XMSLAT
3
4
5
6 MSDATO
7 MSREADY
8 XMSDOE
9
10
11
12
13 EXCKO1
14 EXCKO2
15
16
17
18 to 25 MNT0 to MNT7
26
TE
L 13942296513
27
28
29
30
31
32 to 34 TEST1 to TEST3
35
36
37
38 to 41 SUPDT0 to SUPDT3
42
43, 44 SUPDT4, SUPDT5
45
46, 47 SUPDT6, SUPDT7
48
49
50
51, 52 TEST4, TEST5
53
54
55, 56
www
57 BCKASL
58 VSDSD0
.
59
60
61
http://www.xiaoyu163.com
I/O
VSCA0 — Ground terminal (for core)
I Serial data latch pulse signal input from the mechanism controller
MSCK I Serial data transfer clock signal input from the mechanism controller
MSDATI I Serial data input from the mechanism controller
VDCA0 — Power supply terminal (+2.5V) (for core)
O Serial data output to the mechanism controller
O Ready signal output to the mechanism controller
O Serial data output enable signal output terminal
XRST I Reset signal input from the mechanism controller
Soft muting on/off control signal input from the mechanism controller
SMUTE I
"H": muting on
MCKI I Master clock signal (33.8688 MHz) input
VSIOA0 — Ground terminal (for I/O)
O Master clock signal (33.8688 MHz) output to the digital audio processor
O External clock 2 signal output terminal
LRCK O L/R sampling clock signal (44.1kHz) output terminal
F75HZ O Not used
VDIOA0 — Power supply terminal (+3.3V) (for I/O)
O Monitor signal output terminal
TCK I Clock signal input from the DVD system processor
TDI I Serial data input from the DVD system processor
VSCA1 — Ground terminal (for core)
TDO O Serial data output to the DVD system processor
TMS I TMS signal input from the DVD system processor
TRST I Reset signal input from the DVD system processor
I Input terminal for the test (normally: fixed at "L")
VDCA1 — Power supply terminal (+2.5V) (for core)
UBIT O Not used
XBIT O Not used
O Supplementary data output terminal
VSIOA1 — Ground terminal (for I/O)
O Supplementary data output terminal
VDIOA1 — Power supply terminal (+3.3V) (for I/O)
O Supplementary data output terminal
SUPEN O Supplementary data enable signal output terminal
VSCA2 — Ground terminal (for core)
NC O Not used
I Input terminal for the test (normally: fixed at "L"s)
NC O Not used
VDCA2 — Power supply terminal (+2.5V) (for core)
NC O Not used
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for
I
DSD data output "L": input (slave), "H": output (master)
x ao
y
— Ground terminal (for DSD data output)
i
BCKAI I Bit clock signal (2.8224 MHz) input terminal for DSD data output
BCKAO O Bit clock signal (2.8224 MHz) output terminal for DSD data output
PHREFI I Bit clock signal (2.8224 MHz) input terminal for DSD data output
http://www.xiaoyu163.com
8
Not used
Q Q
3 6 7 1 3
u163
.
2 9 9 4 2 8
Description
"L": ready
Not used
"L": reset
Not used
Not used
1 5 0 5 8 2 9 9 4
"L": reset
Not used
Not used
Not used
Not used
m
Fixed at "H" in this set
co
HCD-SR4W
9 9
2 8 9 9
Not used
Not used
97