Sony HCD-SR4W Service Manual page 95

QQ
3 7 63 1515 0
Pin No. Pin Name
116
117
118, 119 VCCA5, VCCA4
120
121
122, 123 GNDA4, GNDA3
124
125
126, 127 LPF2, LPF1
128, 129 VCCA3, VCCA2
130
131 PDHVCC
132
133, 134 GNDA2, GNDA1
135
136
137
138
139
140
TE
L 13942296513
141
142 MDSOUT
143
144 MDPOUT
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
www
161
162
163
.
164
165
166
http://www.xiaoyu163.com
I/O
RFDCC I Input terminal for adjusting DC cut high-pass filter for RF signal
RFIN I RF signal input from the DVD/CD RF amplifier
— Power supply terminal (+3.3V) (analog system)
VCOR1 — VCO oscillating range setting resistor connected terminal
VCOIN I VCO input terminal
— Ground terminal (analog system)
LPF5 O Signal output from the operation amplifier from PLL loop filter
VC1 I Middle point voltage (+1.65V) input terminal
I Inverted signal input to the operation amplifier from PLL loop filter
— Power supply terminal (+3.3V) (analog system)
PDO O Signal output from the charge pump for phase comparator
I Middle point voltage input terminal for RF PLL
FDO O Signal output from the charge pump for frequency comparator
— Ground terminal (analog system)
SPO O Spindle motor control signal output
VC2 I Middle point voltage (+1.65V) input terminal
MDIN2 I Spindle motor servo drive signal input
MDIN1 I MDP input terminal
VCCA1 — Power supply terminal (+3.3V) (analog system)
CLVS O Control signal output for selection the spindle control filter constant at CLVS
VSS — Ground terminal (digital system)
O Frequency error output terminal of internal CLV circuit
VDD — Power supply terminal (+3.3V) (digital system)
O Phase error output terminal of internal CLV circuit
DFCT I Defect signal input terminal
Guard subcode sync (S0+S1) detection signal input from the digital signal
GSCOR I
processor
EXCK O Subcode serial data reading clock signal output to the digital signal processor
SBIN I Subcode serial data input from the digital signal processor
VSS — Ground terminal (digital system)
SCOR I Sucode sync (S0+S1) detection signal input from the digital signal processor
WFCK I Write frame clock signal input from the digital signal processor
VDD5V — Power supply terminal (+5V)
XRCI I RAM overflow signal input terminal
VDDS — Power supply terminal (+5V) (digital system)
C2PO I C2 pointer signal input from the digital signal processor
VDD — Power supply terminal (+3.3V) (digital system)
DBCK O Bit clock signal (2.8224 MHz) output terminal
BCLK I Bit clock signal (2.8224 MHz) input from the digital signal processor
DDAT O PCM data output terminal
MDAT I Serial data input from the digital signal processor
VSS — Ground terminal (digital system)
DLRC O L/R sampling clock signal (44.1 kHz) output terminal
x ao
y
LRCK I L/R sampling clock signal (44.1 kHz) input from the digital signal processor
i
XRST I Reset signal input from the mechanism controller
IFS0 I Interface selection signal input terminal
IFS1 I Interface selection signal input terminal
http://www.xiaoyu163.com
8
Q Q
3 6 7 1 3
Not used
Not used
u163
.
2 9 9 4 2 8
Description
1 5 0 5 8 2 9 9 4
Not used
Not used
m
Not used
co
"L": reset
Fixed at "L" in this set
Fixed at "H" in this set
HCD-SR4W
9 9
Not used
2 8 9 9
95