Sony HCD-FLX7D Service Manual page 86

HCD-FLX5D/FLX7D
Q Q
3 7 6 3 1 5 1 5 0
• IC Block Diagrams
– RF Board –
IC001 SP3723CAF0PM
64 63 62 61 60 59 58
INPUT
SEL ATT
4
INPUT
DVDRFP 1 MUX ATT AGC
BIAS
DVDRFN 2
2
2
INPUT
INPUT IMPEDANCE
IMPEDANCE SEL
SEL
+
CLAMP &
– ENVELOPE
BUFFER
2
LEVEL
SIGDET
DAC
COMPARATOR
A2 3
PHASE
DETECTOR
B2 4
GCA EQ +
+
C2 5
PHASE
DETECTOR
D2 6
3 T E 3
L 1 3 9 4 2 2 9 6 5 1 3
FROM FROM
VC
S-PORT S-PORT
CP 7
CN 8
A+D
D
D 9 +
+
C
C 10
+
GCA
B
+
B 11
B+C
A
A 12
3
CD/DVD
FROM
MUX
S-PORT
B+D
CD D 13
+
+
CD C 14
SUM
GCA
AMP
W/LPF
CD B 15
+
+
CD A 16
A+C
3
CD/DVD FROM
S-PORT
–
GCA
+
GCA
3 4
FROM FROM
S-PORT S-PORT
VCI FOR SERVO INPUT
VC = VPB/2
w w w
APC SEL
DUAL APC
DVD/CD
LD H/L
FROM S-PORT
17 18 19 20 21 22 23 24 25 26 27
57 56 55 54 53 52 51 50
FAST ATTACK
OUTPUT
FULL WAVE AGC CHARGE
INHIBIT
RECTIFER PUMP
PROGRAMMABLE
FROM S-PORT
EQUALIZER
FILTER
DIFFERENTIATOR
AGCO
CONTROL
SERIAL
SIGNALS
PORT
+ TO EACH
REGISTER
BLOCK
–
V33 FOR
OUTPUT
3 BUFFER
LPF ATT
CE ATT
POL SEL
CEPOL
BUFFER
– –
PI
FE
TE
CE
V25
V125
V25/3
TOPHOLD
–
OFFSET
GCA GCA
+ CANSEL
TOPHOLD
4
FROM
S-PORT
–
OFFSET
GCA LPF GCA GCA
+ CANSEL
GCA
4 5
FROM FROM
S-PORT S-PORT
OFFSET TE
MUX GCA GCA LPF GCA SUB GCA GCA
CANSEL RST
6 3
CP/CN
CEFDB FROM FROM
LOW
S-PORT S-PORT
IMPEDANCE
+
OFFSET
GCA LPF
+ CANSEL
5
FOR SERVO
FROM
OUTPUT
S-PORT
HOLDEN
V25/2
SEL
BCA
TOP
DET
HOLD
COMPA-
RATOR
–
2
FROM
+
DAC
S-PORT
LINKEN
HYSTERESISTER
& OFFSET
FROM S-PORT
INPUT GAIN
INPUT
FROM S-PORT AGCO
IMPEDANCE
2
MIRR
FROM S-PORT
x a o
COMPARATOR SINK CURRENT
2
FROM S-PORT
PEAK/BOTTOM INPUT
INTERNAL
. i
HOLD BUFFER
FDGHG
28 29 30 31
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– MB Board –
IC203 BR9040F-WE2
8
49
4096bit
EEPROM ARRAY
AGC
HOLD
ADDRESS R/W
DECODER AMP
ADDRESS DATA
48 SDEN
BUFFER REGISTER
47 SDATA
46 SCLK
45 V33
44 LCP
1
43 LCN
MNTR
42 MNTR
CONTROL
IC215 SN74ALVCH16841DGGR
Q Q
3 7
41 CE
1OE 1 OE
1D1 2
40 FE
1D2 3
GND 4
1D3 5
1D4 6
39 TE
VCC 7
LATCH
1D5
8
1D6 9
GND 10
38 PI
1D7 11
1D8 12
1D9 13
PH
1D10 14
37 V25
36 V125
2D1 15
2D2
16
35 TPH
2D3 17
GND 18
SEL GCA 34 DFT
2D4 19
2D5 20
2D6 21
33 LINK
LATCH
VCC
22
2D7 23
2D8 24
BOTTOM
GND 25
ENVELOPE
2
2D9 26
u 1 6 3
y
2D10 27
PH
MUX
2OE 28 OE
32
86 86
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2 4
8 9 9
7 6 5
COMMAND
REGISTER
WRITE
DISABLE
POWER
HIGH VOLTAGE
SUPPLY
GENERATOR
VOLTAGE
DETECTOR
COMMAND DECODE
CONTROL CLOCK
GENERATION
2 3 4
6 3 1 5 1 5 0 8 9
LE 56 1LE
55 1Q1
54 1Q2
53 GND
52 1Q3
51 1Q4
50 VCC
49 1Q5
48 1Q6
47 GND
1Q7
46
45 1Q8
44 1Q9
43 1Q10
42 2Q1
41 2Q2
40 2Q3
39 GND
38 2Q4
37 2Q5
2Q6
36
35 VCC
34 2Q7
33 2Q8
m
32 GND
31 2Q9
c o
30 2Q10
.
LE 29 2LE
2
8 9 9
2 4 9 8 2 9 9