Aiwa CSD-A510 Service Manual page 23

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Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
TE
L 13942296513
60
61
62
63
64
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Pin Name I/O
XVDD — Crystal oscillator power supply pin.
XOUT O
Pin to which external 16.9344 MHz crystal oscillator is connected.
XIN I
XVSS — Crystal oscillator GND pin. Be sure to connect to 0V.
SBSY O Subcode block sync signal output pin.
EFLG O C1, C2, single and dual correction monitoring pin.
PW O Subcode P, Q, R, S, T, U and W output pin.
SFSY O Subcode frame sync signal output pin. Falls down when subcode enters standby.
Subcode read clock input pin. Schmidt input. (Be sure to connected to 0V when not
SBCK I
in use.)
Pin outputting the 7.35 kHz sync signal which is generated by dividing frequency of
FSX O
crystal oscillator.
WRQ O Subcode Q output standby output pin.
RWC I Read/write control input pin. Schmidt input.
SQOUT O Subcode Q output pin.
COIN I Command input pin from microprocessor.
___________
CQCK I Command input read clock or subcode read input clock from SQOUT pin
RES I LC78622 reset input pin. Set this pin to L once when the main power is turned on.
T11 O Test signal output pin. Use this pin as open (normally L output).
16M O 16.9344 MHz output pin.
4.2M O 4.2336 MHz output pin.
T5 I Test signal input pin with built-in pull-down resistor. Be sure to connect to 0V.
Chip select signal input pin with built-in pull-down resistor. Be sure to connect to 0V
______
CS I
while it is not controlling.
T1 I Test signal input pin without built-in pull-down resistor. Be sure to connect to 0V.
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