Sony HCD-ZX10D Service Manual page 85

Dvd deck receiver
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3 7 63 1515 0
Pin No.
Pin Name
128, 129
VCCA3, VCCA2
130
131
PDHVCC
132
133, 134
GNDA2, GNDA1
135
136
137
138
139
140
141
142
MDSOUT
143
144
MDPOUT
145
146
147
148
149
150
151
TE
L 13942296513
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172 to 176
D0 to D4
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.
http://www.xiaoyu163.com
I/O
Power supply terminal (+3.3V)
PDO
O
Signal output from the charge pump for phase comparator
I
Middle point voltage input terminal for RF PLL
FDO
O
Signal output from the charge pump for frequency comparator
Ground terminal
SPO
O
Spindle motor control signal output terminal
VC2
I
Middle point voltage (+1.65V) input terminal
MDIN2
I
Spindle motor servo drive signal input terminal
MDIN1
I
MDP input terminal
VCCA1
Power supply terminal (+3.3V)
CLVS
O
Control signal output for selection the spindle control filter constant at CLVS
VSS
Ground terminal
O
Frequency error output terminal of internal CLV circuit
VDD
Power supply terminal (+3.3V)
O
Phase error output of internal CLV circuit
DFCT
I
Defect signal input from the DSP
GSCOR
I
Guard subcode sync (S0+S1) detection signal input from the DSP
EXCK
O
Subcode serial data reading clock signal output to the DSP
SBIN
I
Subcode serial data input from the DSP
VSS
Ground terminal
SCOR
I
Subcode sync (S0+S1) detection signal input from the DSP
WFCK
I
Write frame clock signal input from the DSP
VDD5V
Power supply terminal (+5V)
XRCI
I
RAM overflow signal input terminal
VDDS
Power supply terminal (+5V)
C2PO
I
C2 pointer signal input from the DSP
VDD
Power supply terminal (+3.3V)
DBCK
O
Bit clock signal output terminal
BCLK
I
Bit clock signal input from the DSP
DDAT
O
PCM data output terminal
MDAT
I
Serial data input from the DSP
VSS
Ground terminal
DLRC
O
L/R sampling clock signal output terminal
LRCK
I
L/R sampling clock signal input from the DSP
XRST
I
Reset signal input from the mechanism controller
IFS0
I
Interface selection signal input terminal
IFS1
I
Interface selection signal input terminal
XTAL
I
System clock (33.8688 MHz) input terminal
VSS
Ground terminal
XTL2
O
System clock (33.8688 MHz) output terminal
XTL1
I
System clock (33.8688 MHz) input from the clock generator
VDD
Power supply terminal (+3.3V)
I/O
Two-way data bus with the mechanism controller
x
ao
y
i
http://www.xiaoyu163.com
8
Q Q
3
6 7
1 3
Not used
u163
.
2 9
9 4
2 8
Description
1 5
0 5
8
2 9
9 4
Not used
Not used
Not used
"L": reset
Fixed at "L" in this set
Fixed at "H" in this set
m
co
HCD-ZX10D
9 9
2 8
9 9
85

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