Schematic Diagram - Dsp Board - Sony TA-F501ES Service Manual

TA-F501ES
Q Q
3 7 6 3 1 5 1 5 0
5-13. SCHEMATIC DIAGRAM – DSP Board –
IC4
TC7WH157FK
FLIP-FLOP (TE85R)
SF_CPU_CE∗ 3.3
SF_DSP_CE∗ 3.3
SF_DSP_MAS
3.3
8
DSP_SPICLK 2 6 3.3
3.3
0
1 IC5(1/2)
TC7WH125FK
(TE85R)
SPI_CLK BUFFER
IC5(2/2)
TC7WH125FK
(TE85R)
4
DSP_MOSI 5 3 0
0
7
0
MOSI
DSP_MISO
C36
10
C39
0.1
T E
L 1 3 9 4 2 2 9 6 5 1 3 C26
0.1
1.2
1.2
C28 0.1
1.2
C29 0.1
3.3
C30 0.1
1.2
R21
10k
C25 0.01
1.2
R24
1k
DSP_RESET∗ 3.3
DSP_SPIDS∗ R25 0 3.3
R32 10k C32 0.1
1.2
SPI_CLK R26 22 3.3
DSP_MISO R27 22 3.3
MOSI R28 22 0
C23 0.1
1.2
C33 0.1 3.3
R36 10
1.1
C34 0.1
C24 0.01
R29 22
3.3
R30 22 0.8
R17 0 R20 0 0
R13 0 0
R18 0 0
R16 0 0
C9
1.5
8p
R23
1.6
470
C10
3.3
8p
X1 R35
25MHz 1M C35
0.1
C19
10
C40
0.1
w w w
TA-F501ES
• See page 27 for Waveforms. • See page 39 for IC Block Diagrams.
C3
0.1
3.3 SERIAL FLASH
IC3
0
SST25VF04
R9 R12
-06FAES
0 10k 10k C8
0.1
3.3
3.3
3.3
3.3 3.3
3.3 3.3
0
C5 0.1
R33
10k
R34
10k
R31 R46 R47 R48
R55
10k 22 0 0
0
DSP
IC2
ADSST-AVR-1115
x a o
C45
y
0.1 R49
0
. i
http://www.xiaoyu163.com
• See page 47 for IC Pin Function Description.
FB2
IC1
SI-3010KM-TL
+1.2V REGULATOR
2.4 1.2
2.3 1
R14
2k R1
R5 0.33
10k
R2
C7
10k C6
C1
C12 R15 100
82 0.1
0.1 10k 2V
4V
R60
22
C71
0.1
C85
10
Q Q
3 7 6
1.2
R64
22
SO_D
0
SO_C
0
R65
22
1.2
1.2 C73 0.1
R66
22
SO_B
0
1.6 R67 22 SO_A
0
SF_DSP_MAS
C74 R68
0.1 22
1.2
3.3
RB1
0
0 C75 0.1
A18
0
A17 C88
0.1
A16
1.2 C76 0.1
ALE
0 AD15
0 AD8 AD14
0 AD9
0 AD10 AD13
0
AD11 AD12
1.2 C77 0.1
AD11
0
AD12 AD10
3.3
AD9
0 C78 0.1
AD13 AD8
0
AD14 AD7
0
AD15 AD6
0 R62 0
ALE
3.3
RD∗ AD5
R63 AD4
0
1.2
AD3
AD2
C80
82
4V
C79
AD1
0.1
AD0
ALE
C81
100
C67 2V R3
0.1 0.33
u 1 6 3
R61 C70
C63 0 10
0.1
28 28
http://www.xiaoyu163.com
2 4
8 9 9
FB1
(Page MAIN
A
C11
0.1 23)
CN1
50P
50 PWR_EXT
48 PWR_EXT
46 PWR_INT
44 PWR_INT
42 GND
40 GND
SO_B
38 SO_B
SO_D
36 SO_D
DSP_LRCK
34 DSP_LRCK
32 GND
30 RESERVED
28 GND
SI_B
26 SI_B
SI_D
24 SI_D
LRCK
22 LRCK
20 GND
BCK
18 BCK
16 GND
DSP_INT
14 DSP_INT
DIR_RERR
12 DIR_RERR
10 RESERVED
SF_CPU_CE∗
3 1 5 1 5 0 8 9 2
8 SF_CPU_CE∗
DSP_MOSI
6 DSP_MOSI
SF_DSP_MAS
4 SF_DSP_MAS
2 GND
FB3
RD*
C91 IC6
10 MC74LCX16373DTR2
0 0 RB6
47
A0
0 0
A15
A1
0 0
A14
A2
A13
A3
0 0 A12
A4
0 0
R69
3.3 3.3 RB7
C89 C92
47 AD0
0.1 0.1
0
0
A11
AD1
0
0
A10
AD2
A9
AD3
0
0
A8
RB10
0 0 33
0 0
A7
AD4
0 0
A6
AD5
A5
AD6
0
0 A4
AD7
0
0
RB8
WR*
3.3 3.3 47
C90 C93
A5
0.1 0.1
0 0
A3
A6
0
0 A2
A7
A1
A8
0 0
A0
A16
0 0
RB9
0 0 47
m
c o
ADDRESS LATCH
.
2
8 9 9
2/5
PWR_EXT 49
PWR_EXT 47
PWR_INT 45
PWR_INT 43
GND 41
GND 39
SO_A
SO_A 37
SO_C
SO_C 35
SO_E
SO_E 33
GND 31
DSP_BCK
DSP_BCK 29
GND 27
SI_A
SI_A 25
SI_C
SI_C 23
SI_E
SI_E 21
GND 19
MCK
MCK 17
GND 15
DSP_RESET∗
DSP_RESET∗ 13
DIR_NONAU
DIR_NONAU 11
RESERVED 9
4 9 8 DSP_SPIDS∗ 2 9 9
DSP_SPIDS∗ 7
DSP_MISO
DSP_MISO 5
DSP_SPICLK
DSP_SPICLK 3
GND 1
C94 C95
FB4 0.1 10
0 0 A10
0 0 A9
0 0 A15
0
3.3
0
0 RB12
33
0 AD15
0 AD14
0 AD13
0 AD12
3.3
C96
3.3
0.1 RB13
33
0 0 C97 0.1 AD11
0 0 AD10
RB11 33 0 AD9
0
AD8
0 0
0 A18
3.3
0 0 A14
A13
0 0
0 0 A12
0 0 A11
0 0 A17
IC7
IS61LV6416-10TLT
S-RAM