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MOTOROLA
FUNCTIONAL DESCRIPTION
2.
FUNCTIONAL DESCRIPTION
The board is constructed on a six-layer printed circuit board
(PCB).
See Figure 1 for the functional block diagram and Figure 2
for the board's component location.
1. GENERAL
The VRM
500 board uses the following components:
68HCIIAI microcontroller running at 9.8304
MHz. This gives a bus clock of about 2.45 MHz.
The CPU interprets commands and controls the
data link protocol.
MDD5001 ASIC, integrated system peripheral,
providing
memory
management,
bus
multiplexing, reset control, and additional parallel
I/O for the 68HC 11.
2.1
BOARD INTERFACE
DSP56156 (Digital Signal Processor), responsible
for controlling data transfer to and from the
communication channels under the 68HC 11
control.
68HCll and DSP external memories (128 kB and
32kB RAM).
256 kB Flash EEPROM.
Rechargeable lithium battery, capable of backing
up the 128 kB RAM for at least three days.
Two UARTs (Universal Asynchronous Receiver
Transmi tter).
Serial ADC (Analog to Digital Converter).
Communication and power LEDs.
The
board operates using a nominal 13.8±20%
V
DC from
the radio and regulates it to 5.0
V
DC logic supply
(Vee).
The board includes the following interfaces:
•
DTE - terminated by a DB9 female connector
•
Auxiliary communication - terminated by a DB-9
male connector
•
DTE CMOS level - terminated by an
8-pin'
connector
,.
•
Serial/parallel radio - terminated by a 13-pin
connector.
Power is supplied via the radio connector. Depending on the
DTE installed, the interface conforms either to RS-232 or to
TTL levels.
See paragraphs 2.1.1 to 2.1.4 for a description of the
connector pin functions.
©
Motorola Inc., 1995
Land Mobile Products Sector
1301 E. Algonquin Road, Schaumburg, IL 60196
68P02943C73-0
July, 1995
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