Patton electronics 2040 Series User Manual page 9

2040MT-MC DIP SWITCH SUMMARY TABLE
Position
S1-1
S1-2
S1-3
Table 2. DIP Switch S1 Default Settings for Model 2040MT-MC
Switches S1-1 and S1-2: Gapped Clock
Switches S1-1 and S1-2 allow the Model 2040MT-MC to generate
a HSSI gapped clock. Gapped clocking is a method of flow control in
which data flow is interrupted by an idle (gapped) clock signal. In this
mode, the Model 2040MT-MC will gap the ST clock to the HSSI DTE
whenever the V.35 (or RS-422) CTS signal is de-asserted. In the 'No
Gapped Clock' setting, the V.35 clock passes through with only a level
change.
S1-1 S1-2
Off Off
Off On
On Off
On On
Switches S1-3 and S1-4: Synchronization Method
Switches S1-3 and S1-4 allow the Model 2040MT-MC to
compensate for timing delays when transmitting HSSI data at high
speeds (greater than 2.5 Mbps). At high bit rates, set Switch S1-3 On
and Switch S1-4 Off. In this setting, the V.35 (or RS-422) data signals
will be synchronized to the SD timing signal before conversion to HSSI.
At lower bit rates (less than 2.5 Mbps), set Switch S1-3 Off and S1-4
On. In this setting, the V.35 (or RS-422) data bypasses the
synchronization circuit and is passed straight through to the HSSI DTE.
S1-3 S1-4
Off Off
Off On
On Off
Function
Gapped Clock
Gapped Clock
Sync Method
Description
Not a Valid Setting
Gapped Clock
No Gapped Clock
Not a Valid Setting
Description
Not a Valid Setting
Data Skips Sync Circuit
Data passes through sync circuit.
8
Factory Default
On
}
No Gapped
Clock
Off
Off
}
Bypass
Sync Circuit