Pci Timing Settings; Integrated Peripherals - JETWAY P4MDMR7A User Manual

CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
AGP Transfer Aperture Size
AGP Mode
AGP Driving Control
* AGP Driving Value
AGP Fast Write
AGP Master 1 WS Write
AGP Master 1 WS Read
CPU to AGP Post Write
AGP Delay Transaction
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
Note: Change these settings only if you are familiar with the chipset.

3-6-3 PCI Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
PCI Master 1 WS Write
PCI Master 1 WS Read
CPU to PCI Write Buffer
PCI Delay Transaction
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.

3-7 Integrated Peripherals

CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
> OnChip IDE Function
> OnChip Device Function
> Onboard Super IO Function
Init Display First
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
OnChip IDE Function
AGP Timing Settings
64M
Auto
Auto
DA
Disabled
Enabled
Enabled
Disabled
Disabled
F6:Optimized Defaults
PCI Timing Settings
Disabled
Disabled
Enabled
Disabled
F6:Optimized Defaults
Integrated Peripherals
Press Enter
Press Enter
Press Enter
PCI Slot
F6:Optimized Defaults
26
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F7:Standard Defaults
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F7:Standard Defaults
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F1:General Help
F7:Standard Defaults