MSI K8T Neo-FSR User Manual page 61

(v1.x) atx mainboard
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MS-6702 ATX Mainboard
Bank Interleaving
This field selects 2-bank or 4-bank interleave for the installed SDRAM. Dis-
able the function if 16MB SDRAM is installed. Settings: Disabled, 2-Way
and 4-Way.
Burst Length
This setting allows you to set the size of Burst-Length for DRAM. Bursting
feature is a technique that DRAM itself predicts the address of the next memory
location to be accessed after the first address is accessed. To use the feature,
you need to define the burst length, which is the actual length of burst plus the
starting address and allows internal address counter to properly generate the
next memory location. The bigger the size, the faster the DRAM performance.
Settings: 4 QW and 8 QW.
CAS Latency (CL)
This controls the timing delay (in clock cycles) before SDRAM starts a read
command after receiving it. Settings: 2, 2.5, 3 (clocks). 2 (clocks) increases
the system performance the most while 3 (clocks) provides the most stable
performance.
TRCD
When DRAM is refreshed, both rows and columns are addressed separately.
This setup item allows you to determine the timing of the transition from RAS
(row address strobe) to CAS (column address strobe). The less the clock
cycles, the faster the DRAM performance. Settings: 2T to 5T.
TRAS
This setting determines the time RAS takes to read from and write to a memory
This setting determines the time RAS takes to read from and write to a memory
This setting determines the time RAS takes to read from and write to a memory
This setting determines the time RAS takes to read from and write to a memory
This setting determines the time RAS takes to read from and write to a memory
cell. Setting options:
cell. Setting options:
cell. Setting options:
cell. Setting options:
cell. Setting options:
TRP
This setting controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If insufficient time is allowed for the RAS to accumu-
late its charge before DRAM refresh, refresh may be incomplete and DRAM
may fail to retain data. This item applies only when synchronous DRAM is
installed in the system. Setting options: 2T to 5T.
3-12
4 T 4 T 4 T 4 T
9 T 9 T 9 T 9 T
t o t o t o t o
. . . .
4 T
t o
9 T
.

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