BenQ PB6100 Service Manual page 104

A
INPUT
4
VDD
VDD
3.3V
3.3V
CHROMA CHROMA
CHROMA
LUMA LUMA
LUMA
CVBS CVBS
CVBS
3
SDA
SCL
RAIN_C RAIN_C
RAIN_C
GAIN_C GAIN_C
GAIN_C
BAIN_C BAIN_C
BAIN_C
VSYNC_C VSYNC_C
VSYNC_C
HSYNC HSYNC
HSYNC
2
VDD
3.3V
CONTROL
CONTROL
1
RXD
RXD
TXD
TXD
011_INPUT
A
B
DECODE
VDD
012_DECODE
VDD
V33
V33
LLC1
LLC2
VY[7:0]
SDA VY[7:0]
SCL
VUV[7:0]
VUV[7:0]
CHROMA
VVS
VVS
VFIELD
LUMA VFILD
VPEN
VPEN
VHS
CVBS VHS
VCLK
VCLK
GND
V33
V33
SDA
GRE[7:0]
SCL GRE[7:0]
GGE[7:0]
GGE[7:0]
GBE[7:0]
GBE[7:0]
GHS
GHS
GVS
GVS
GBLKSPL
GBLKSPL
GFBK
RAIN_C GFBK
GCLK
GAIN_C GCLK
GCOAST
BAIN_C GCOAST
VDD
VSYNC_C
VDD
HSYNC
GND
PAGE_8
013_AFE
RESETn
RESETn
D[0:7]
D[0:7]
CS1n
CS1n
CS0n
VDD CS0n
key8
3.3V
GND
PAGE_12
017_KEY
B
C
014_MEMORY&KEYSTONE
PAGE_9
VDD
RESETn
3.3V
SCL
SCL
SDA
SDA
GND
VY[7:0]
VY[7:0]
VUV[7:0]
VUV[7:0]
VVS
VVS
VFIELD
VFIELD
VPEN
VPEN
VHS
VHS
VCLK
VCLK
SCL
SCL
SDA
SDA
GRE[7:0]
GRE[7:0]
GGE[7:0]
GGE[7:0]
GBE[7:0]
GBE[7:0]
GHS
GHS
GVS
GVS
GBLKSPL
GBLKSPL
GFBK
GFBK
GCLK
GCLK
GCOAST
GCOAST
CS1n
CS1n
CS0n
CS0n
key8
IRR CVR
RXD
TXD
C
D
Regect RC1 and RC2 before connect DX660 main board with
INTERFACE board.
VDD
VDD
3.3V
3.3V
GND
PAGE_11
016_MISC
POWERON
RESETZ
DRO[7:0]
DRE[7:0]
DGO[7:0]
DGE[7:0]
DBO[7:0]
DBE[7:0]
DHS
DVS
DEN
DCLK
LAMPLITZ
ECO-MODE
FAN_P
VDD
3.3V
GND
PAGE_10
015_PW166
Benq Corporation
Project Code
99.J8677.001
Title
Size
PCB P/N
<Size>
48.J8601.S04
Tuesday, October 07, 2003
Date:
Prepared By
ANGEL HU
D
E
SCL
SCL
SDA
SDA
GND
4
3.3V 3.3V
VDD
VDD
POWERON
POWERON
RESETZ
RESETZ
DRE[7:0]
DRE[7:0]
DGE[7:0]
DGE[7:0]
3
DBE[7:0]
DBE[7:0]
D HS
DHS
DVS
DVS
D EN
DEN
DCLK
DCLK
Note: To DDP1000 input port
LAMPLITZ
LAMPLITZ
Note: Lamp on/off detect signal.
Note: PW164B RS232 I/O port connect with
PC ( for control ) and Ballast ( for lamp
stasus )
ECO-MODE
ECO-MODE
2
FAN_P
FAN_P
VDD
3.3V
Model Name OEM/ODM Model Name
<OEM/ODM>
PB6100
1
MAIN BOARD
PCB Rev. Document Number R ev.
1
S04 99.J8677.B12-C3-304-004
Sheet 2 o f 20
Reviewed By Approved By
DAVID HN LIN KELVIN LIAO
E