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A/D CONVERTER
A simplified circuit diagram of the analog portion of
the A/D converter is shown in Figure 2. Each of the
switches shown represent analog gates which are
operated by the digital section of the A/D converter.
Basic timing for switch operation is keyed by an
external oscillator.
continuously repeated. A complete cycle is shown
in Figure 2.
Any given measurement cycle performed by the A/D
During autozero, a ground reference is applied as an
input to the A/D converter. Under ideal conditions the
output of the comparator would also go to zero.
However, input-offset-voltage errors accumulate in the
amplifier loop, and appear at the comparator output as
an error voltage. This error is impressed across the AZ
capacitor where it is stored for the remainder of the
measurement cycle. The stored level is used to provide
offset voltage correction during the integrate and read
periods.
The integrate period begins at the end of the autozero
period. As the period begins, the AZ switch opens and
the INTEG switch closes. This applies the unknown
input voltage to the input of the A/D converter. The
voltage is buffered and passed on to the input of the
A/D converter. The voltage is buffered and passed on
to the integrator to determine the charge rate (slope) on
the INTEG capacitor. At the end of the fixed integrate
period, the capacitor is charged to a level proportional
to the unknown input voltage. This voltage is translated
to a digital indication by discharging the capacitor at a
The conversion process is
EXTERNAL
INPUTS
READ
+REF
(FLYING
CAPACITOR)
INTEG
UNKNOWN
INPUT
VOLTAGE+
AZ
INTEG
AZ
0
COUNTER OUTPUT
166.7mS
Figure 2 Dual Slope A/D Converter
converter can be divided into three consecutive time
periods: autozero (AZ), integrate (INTEG) and read.
Both autozero and integrate are fixed time periods.
A counter determines the length of both time
periods by providing an overflow at the end of every
1,000 clock pulses. The read period is a variable
time, which is proportional to the unknown input
voltage. The value of the voltage is determined by
counting the number of clock pulses that occur
during the read period.
BUFFER
INTEGRATOR
AMP
AZ
INTEG.
READ
+.20
.15
.10
.05
0
10,000
500
1000
1500
0
fixed rate during the read period, and counting the
number of clock pulses that occur before it returns to
the original autozero level.
As the read period begins, the INTEG switch opens and
the read switch closes. This applies a known reference
voltage to the input of the A/D converter. The polarity
of this voltage is automatically selected to be opposite
that of unknown input voltage, thus causing the INTEG
capacitor to discharge as fixed rate (slope). When the
charge is equal to the initial starting point (autozero
level), the read period is ended. Since the discharge
slope is fixed during the read period, the time required
is proportional to the unknown input voltage.
The autozero period and thus a new measurement
cycle begins at the end of the read period. At the same
time, the counter is released for operation by
transferring its contents (previous measurement value)
to a series of latches. This stored stat is then decoded
and buffered before being used for driving the LCD
display.
-2-
COMPARATOR
AZ
TO
DIGITAL
CONTROL
LOGIC
AZ
2000
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