Table of Contents
Advertisement
Xilinx System Generator v2.1 Reference Guide
Block Parameters Dialog Box
The block parameters dialog box can be invoked by double-clicking the icon in your
Simulink model.
Figure 3-66: Threshold block parameters dialog box
The block parameters do not control the output data type because the output is
always a signed fixed point integer that is 2 bits long.
All the parameters used by this block are explained in the Common Parameters
section of the previous chapter.
The Threshold block does not use a Xilinx LogiCORE.
MATLAB I/O
The MATLAB I/O section includes Xilinx Gateway blocks, the Enabled Subsystem
gateway, blocks to report quantization error, and display blocks.
Gateway Blocks
The Xilinx Gateway blocks have several functions:
Enabled Subsystems
The System Generator infers clock circuitry in its hardware implementation from the
sample periods defined in the Simulink model for the Xilinx blocks. This circuitry
includes clock (CLK), clock enable (CE), and clear (CLR) ports on registers and Xilinx
96
Convert data from double precision floating point to the System Generator fixed
point type and vice versa during Simulink simulation.
Define I/O ports for the top level of the HDL design generated by System
Generator. A Gateway In block defines a top level input port, and a Gateway Out
block defines a top level output port.
Define testbench stimuli and predicted output files when the System Generator
Create Testbench option is selected. In this case, during HDL code
generation, Simulink simulation values are logged as logic vectors into a data file
for each top level port defined by a Gateway block. An HDL component is
inserted in the top level testbench for each top level port which, during HDL
simulation, reads the values from the file and compares them to the expected
results.
The name specified for the Gateway In or Gateway Out block is passed on as the
port name on the top level VHDL entity.
Xilinx Development System
Advertisement
Table of Contents
