Xilinx System Generator V2.1 Reference Manual page 24

Xilinx System Generator v2.1 Reference Guide
Block Parameters Dialog Box
The block parameters dialog box can be invoked by double-clicking the icon in your
Simulink model.
Figure 3-1: System Generator block parameters dialog box
Parameters specific to the System Generator block are:
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Xilinx Product Family
Supported families currently are: Virtex, Virtex2, Spartan2, and VirtexE.
Target Directory
Specify where the output files (VHDL, cores, and project files) will be written. It is
suggested that you create a separate directory (away from your Simulink model
files) to generate your files in order to keep your Xilinx project files and Simulink
model files directories organized separately.
System Clock Period
Enter the desired System Clock Period of your design in nanoseconds (ns). This
information will be passed to the Xilinx software tools through the user
constraints file (.ucf) that will be created by the System Generator. This value
will be used as the global PERIOD constraint and multi-cycle paths will be
constrained to a multiple of this value.
Create Testbench
Checking the Create Testbench box instructs the tool to save test vectors to be
used downstream, during behavioral simulation.
When the Create Testbench box is checked, a VHDL testbench wrapper file is
created for your design. Data vectors (created during Simulink simulation) are
also generated.
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