Xilinx System Generator V2.1 Reference Manual page 105

Xilinx LogiCORE
The block uses the Xilinx LogiCORE: Dual Port Block Memory v3.2 The address
width must be equal to
where d denotes the memory depth.
The tables below show the widths that are acceptable for each depth.
Table: Maximum Width for Various Depth Ranges (Virtex/Virtex-E)
Table: Maximum Width for Various Depth Ranges (Virtex-II)
The Core datasheet can be found on your local disk at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemdp_v3_2\do
c\dp_block_mem.pdf
Memory
Depth Width
2 to 512
513 to 1024
1025 to 2048
2049 to 4096
4097 to 8192
8193 to 16K
16K+1 to 32K
32K+1 to 64K
64K+1 to 128K
128K+1 to 256K
Depth
2 to 512
513 to 1024
1025 to 2048
2049 to 4096
4097 to 8192
8193 to 16K
16K+1 to 32K
32K+1 to 64K
64K+1 to 128K
128K+1 to 256K
256K+1 to 512K
512K+1 to 1024K
log d
2
256
256
256
192
96
48
24
12
6
3
Width
256
256
256
192
96
48
24
12
6
3
6
3
Xilinx Blocks
105