Memory; Dual Port Ram - Xilinx System Generator V2.1 Reference Manual

Xilinx System Generator v2.1 Reference Guide

Memory

This section contains Xilinx blocks that use Xilinx memory LogiCOREs.

Dual Port RAM

Block Interface
The block has two independent sets of ports for simultaneous reading and writing.
Each port set has one output port and three input ports for address, input data, and
write enable (WE). The Dual Port RAM block supports various Form Factors,
FF = W
The Dual port RAM block allows FF of 1, 2, 4, 8, 16 for Virtex and 1, 2, 4, 8, 16 or 32 for
Virtex-II device families, provided that:
Mod [ ( D
where
D
A
The Depth of port B (D
D
A
The data input ports on Port A and B can have different arithmetic type and binary
point position for a form factor of 1. For form factors greater than 1, the data input
ports on Port A and Port B should have an unsigned arithmetic type with binary point
at 0. The output ports, labeled A and B, have the same types as the corresponding
input data ports.
The location in the memory block can be accessed for reading or writing by providing
the valid address on each individual address port. A valid address is an unsigned
integer from 0 to d-1, where d denotes the RAM depth (number of words in the RAM)
for the particular port. An attempt to read past the end of the memory is caught as an
error in simulation. The initial RAM contents can be specified through a block
parameter. Each write enable port must be a 1-bit unsigned integer. When the WE port
is 1, the value on the data input is written to the location indicated by the address line.
The output during a write operation depends on the write mode. When the WE is 0,
the output port has the value at the location specified by the address line. Write
contention results in data being not written to the memory location and the
corresponding outputs are flagged as invalid. During a write operation (WE asserted),
the data presented on the input data port is stored in memory at the location selected
102
The Xilinx Dual Port RAM block implements a random access
memory (RAM).
/ W where W is data width of Port B and W
B A B
x W ) , W ] = 0 for a given FF
A A B
: Depth specified for Port A
) is inferred from the specified form factor as follows: D
B
/ FF.
is Data Width of Port A.
A
Xilinx Development System
=
B