Switch Settings (Ni 781Xr/783Xr Only) - National Instruments NI 784xR User Manual

PXI Star*
LBLStar0
LBLStar1
LBLStar2
LBLStar3
Slot 2
1
* A Slot 2 device ties the PXI Star Line to the PXI 10 MHz clock
1 Shared Local Bus Lines between Slot 2 and Slot 3
2 Shared Trigger Lines between Slot 2, Slot 3, and Slot 4
3 Shared Local Bus Lines between Slot 3 and Slot 4

Switch Settings (NI 781xR/783xR Only)

Note SW2 and SW3 are not connected.
© National Instruments Corporation
PXI Star
LBLStar0
LBR0
LBR1 LBLStar1
LBR2 LBLStar2
LBR3 LBLStar3
Figure 2-12. PXI Star Trigger Connections in a PXI Chassis
Refer to the PXI Hardware Specification Revision 2.1 and PXI Software
Specification Revision 2.1 at
PXI triggers.
Refer to Figure 2-13 for the location of switches on the NI PCI-781xR and
Figure 2-14 for the location of switches on the NI PXI-781xR. Refer
to Figure 2-15 for the location of switches on the NI PCI-783xR and
Figure 2-16 for the location of switches on the NI PXI-783xR. For normal
operation, SW1 is in the OFF position. To prevent a VI stored in flash
memory from loading to the FPGA at power up, move SW1 to the
ON position, as shown in Figure 2-17.
Chapter 2
PXI Star
LBR0 LBLStar0
LBR1 LBLStar1
LBR2 LBLStar2
LBR3 LBLStar3
Slot 3
www.pxisa.org
2-23
Hardware Overview of the NI 78xxR
LBR0
LBR1
LBR2
LBR3
Slot 4
for more information about
R Series Intelligent DAQ User Manual
2
3